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[Seminar] Exploring the Speed-Accuracy-Power Limits of Nyquist ADC Architectures

Source:     Publish Date:2022-09-26     Page Views:

Title:Exploring the Speed-Accuracy-Power Limits of Nyquist ADC Architectures

SpeakerProf. Filip Tavernier

                  KU Leuven

HostProf. Tang Xiyuan

Date & Time2022/09/29 16:00 - 17:00

Zoom: 899 8555 4110 (Passcoe: 019031)


Abstract:   

In this talk, I will discuss the well-known trade-off between speed, accuracy, and power consumption of Nyquist ADCs. To compare different architectures, I will introduce a framework capturing the most significant effects and trade-offs on a building block level which eventually impact the overall ADC performance. Moreover, I will incorporate the effects of technology scaling by considering the most significant technology parameters of several popular CMOS technologies. To conclude, I will use the presented framework to compare the most popular ADC architectures at different sample rates.


Biography:

Filip Tavernier is a professor in the MICAS research division of the Department of Electrical Engineering of KU Leuven since October 2015. His main research interests are analog and mixed-signal integrated circuits for high-performance data converters, DC-DC converters, optical receivers, and cryogenic circuits. He obtained his Ph.D. degree from KU Leuven in 2011. He is a past member of the microelectronics group at CERN in Geneva, Switzerland, as a senior fellow, developing chips for the LHC experiments. He is a TPC member of ESSCIRC and CICC and volunteers in the SSCS Benelux Chapter and is SSCS European Webinar Coordinator.