At the end of February 2022, the IEEE International Solid-State Circuits Conference (ISSCC), also known as the "Integrated Circuit Olympics," was successfully held. ISSCC is recognized as the highest-level conference in the field of integrated circuit design by the academic and industrial communities worldwide.
During this conference, an academic article titled "A 1.041Mb/mm2 27.38TOPS/W Signed-INT8 Dynamic Logic Based ADC-Less SRAM Compute-In-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications" by the research group led by Academician Huang Ru and Assistant Professor Yan Bonan of the School of Integrated Circuits,Peking University and the Institute for Artificial Intelligence,Peking University, was included in the special session, "Session11 Compute-In-Memory and SRAM" (paper number 11.7).
This work proposes an efficient ADC-less SRAM Compute-In-Memory acceleration engine with a high-energy efficiency ratio of 27.38TOPS/W@INT8 and a density of 1.041Mb/mm2, based on the 28nm process technology. It has achieved international leading indicators and technological breakthroughs.
The collaborators of this work include Pimchip Technology Co., Ltd., NeoNexus Group, and Duke University. The research group has received support from the Institute for Artificial Intelligence, Peking University and Pimchip Technology, among others.
Attached is a brief introduction to this work and the research group:
Digital Compute-In-Memory Technology Path
This work realizes a 32Kb ADC-less SRAM Compute-In-Memory acceleration unit at the 28nm technology node, which replaces traditional analog-to-digital conversion or CMOS static logic with dynamic logic computation circuits, achieving high energy efficiency and area efficiency. The reconfigurable local processing units (RLPUs) distributed within the memory array enable bitcell-level array logic operations and expand to vector matrix multiplication (VHP/VMM). In terms of core indicators, it has significant advantages over traditional architectures, laying a solid foundation for the practical industrial deployment of Compute-In-Memory technology.
Compute-In-Memory Chip Demonstration
Compute-In-Memory chips are mainly used for accelerating massive multiply-accumulate operations in deep learning networks. The research group has conducted practical demonstrations of common neural networks using prototype chips, receiving wide acclaim during the demonstration session at ISSCC. The demonstration video link can be found at:
https://www.bilibili.com/video/BV15b4y1H7gP
Introduction to Academician Huang Ru and Assistant Professor Yan Bonan's Research Group
Assistant Professor Yan Bonan received his Ph.D. in Electronics and Computer Engineering from Duke University in 2020. He later joined the Institute for Artificial Intelligence, Peking University to conduct research at the intersection of artificial intelligence and chip technologies. His main research areas include:
- Emerging memory integrated circuit design
- Circuit and system integration of storage and computation
- Microarchitecture for artificial intelligence computing
The research group constantly recruits undergraduate and graduate students who are eager to explore the unknown and innovate. For collaboration and admission-related inquiries, please contact via email: bonanyan@pku.edu.cn.
Introduction to ISSCC Conference
The IEEE International Solid-State Circuits Conference (ISSCC) is recognized as the highest-level conference in the field of integrated circuit design by the academic and industrial communities. It is regarded as the "Olympic Games" of integrated circuit design. Numerous milestone inventions in integrated circuit history, such as the world's first TTL circuit, first 8-bit microprocessor, first 1Gb DRAM, first GHz microprocessor, and first multi-core processor, were unveiled at this conference. Since its inception in 1954, the conference has been successfully held for 68 sessions. The selection of this Compute-In-Memory paper indicates that this core technology has reached an international leading level and has received recognition from top academic conferences. It represents a new direction in the field of chip design and has tremendous development prospects in the era of continuously advancing AI technology.
