Yaoyu Tao received his BSE in computer engineering from Shanghai Jiao Tong University, M.S. in electrical engineering from Stanford University, and Ph.D. degree in electrical engineering from University of Michigan, Ann Arbor. He also worked as staff ASIC engineer in Qualcomm wireless R&D and senior design engineer in Oracle VLSI group. He is currently an assistant professor in the School of Integrated Circuits as well as the Institute of Artificial Intelligence. His research interests include: 1) algorithm-architecture co-design for in-memory computing systems and neuromorphic computing systems using memristor devices; 2) Moire superlattice devices and their hardware applications. In academia, he has published papers in top-tier architecture and circuits journals and conferences such as JSSC, VLSI, ISSCC, and MICRO. In industry, he has led or participated in several AI chip designs and IoT chip designs with multiple granted patents.
Awards:
1) Best paper award, IEEE Globecom 2021
2) Best paper nomination, IEEE VLSI 2019
2) Qualstar awards, Qualcomm, 2019, 2020, 2021
3) Rackham research award, University of Michigan, 2018
4) First prize, Circuits design contest, Analog Devices & Stanford University
5) Best paper nomination, IEEE ISCAS 2013
Selected Publications:
1. Yaoyu Tao; Sung-Gun Cho; Zhengya Zhang; A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture, IEEE Journal of Solid-State Circuits (JSSC), 2020, 56(2): 612-623.
2. Yaoyu Tao; Zhengya Zhang; HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer, 2021 IEEE/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece, 2021-10-18 to 2021-10-22.
3. Yaoyu Tao; Zhengya Zhang; DNC-Aided SCL-Flip Decoding of Polar Codes. In2021 IEEE Global Communications Conference (GLOBECOM), Madrid, Spain, 2021 Dec 7. (Best paper award)
4. Yaoyu Tao; Sung-Gun Cho; Zhengya Zhang; A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS, 2019 Symposium on VLSI Circuits (VLSI), Kyoto, Japan, 2019-5-29 to 2019-6-1. (Best paper nomination)
5. Yaoyu Tao; Shuanghong Sun; Zhengya Zhang; Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes, IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2019, 66(10): 4032-4043.
6. Yaoyu Tao; Joyce Kwong. "LDPC post-processor architecture and method for low error floor conditions." U.S. Patent No. 9,793,923. 17 Oct. 2017.
7. Junkang Zhu*; Yaoyu Tao*; Zhengya Zhang. "eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs." In 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 802-813. IEEE, 2023. (Co-first author)
8. Youn Sung Park; Yaoyu Tao; Zhengya Zhang. "A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating." IEEE Journal of Solid-State Circuits (JSSC) 50, no. 2 (2014): 464-475.
9. Youn Sung Park, Yaoyu Tao; Zhengya Zhang. "A 1.15 Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating." In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 422-423. IEEE, 2013.
10. Youn Sung Park; Yaoyu Tao; Shuanghong Sun; Zhengya Zhang. "A 4.68 Gb/s belief propagation polar decoder with bit-splitting register file." In 2014 Symposium on VLSI Circuits Digest of Technical Papers (VLSI), pp. 1-2. IEEE, 2014.
11. Lei Cai; Jing Wang; Lianfeng Yu; Bonan Yan; Yaoyu Tao*; Yuchao Yang*; Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search, The 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, USA, 2023-2-12 to 2023-2-14.
